The present invention relates to an EMS (Electromagnetic susceptibility) analysis method and EMS analysis apparatus and a method for manufacturing semiconductor devices using the EMS analysis apparatus, and in particular to a method for performing high-speed and high-accuracy EMS analysis on an LSI (Large-scale Integration) circuit featuring large-scale integration and high-speed driving to analyze direct EMS caused by electromagnetic radiation and indirect EMS caused by a power source.
As semiconductor integrated circuits have become faster and achieve larger packing densities, EMS (Electromagnetic susceptibility) has become a serious problem where semiconductor integrated circuits malfunction due to external noises.
One of the possible causes of EMS is that a noise external to a semiconductor integrated circuit entering a power line is propagated inside the semiconductor integrated circuit, affecting signal lines and functional elements, thus causing malfunction of the circuit. Conventionally, tests have been conducted in the design stage to simulate a noise in the signal line of a semiconductor integrated circuit by using a circuit simulator or a faster delay simulator and to check whether such a noise could cause malfunction of the circuit, in order to analyze malfunction caused by a noise entering the semiconductor integrated circuit.
Methods for analyzing a noise other than the EMS noise includes a method for analyzing a crosstalk noise between signal wires in an LSI circuit. As an example of such a method, a method is proposed for analyzing a noise propagated to the circuit elements of the victim caused by a variation in the signal output from the circuit elements of the aggressor due to a coupling capacitance between parallel signal lines thereby analyzing a noise between signal wires, as shown in FIG. 35 (Japanese Patent Publication No. Hei. 6-243193). This technology does not consider the influence that occurs between a power line and a signal line so that it is impossible to analyze the EMS noise.
As shown in FIG. 36, it is possible to input a signal S containing a noise to a power source by using a transistor level simulator such as SPICE. However, in order to locate a disturbance leading to malfunction, it is necessary to perform a large number of test patterns, check the output signals at the circuit elements (gates) and conforming that values different from the expected ones are obtained.
That is, it is necessary to provide test probes for all the cells in order to locate the disturbance. This work is quite difficult in the case of an LSI circuit.
Even when the disturbance is located, which gate must be modified is unknown.
To accurately locate the disturbance, it is necessary to place the LSI circuit in the operating state while using a large number of test vectors.
The aforementioned related art requires huge simulation time for an LSI circuit. The technology considers the case where a noise is generated in a signal line due to a variation in a signal caused by circuit elements in the circuit, or a crosstalk noise, but not the case where a noise is generated in a power line, that is, the influence of indirect EMS on the interior of a semiconductor integrated circuit, or where a noise is generated inside a semiconductor integrated circuit caused by electromagnetic radiation, that is, direct EMS. It is difficult to analyze how the EMS affects a semiconductor integrated circuit and how a circuit is to be modified to cope with the EMS.
As the circuit scale becomes larger, the semiconductor integrated circuit is facing a serious problem of malfunction due to an external power noise (indirect EMS) or a radiation noise due to electromagnetic waves (direct EMS). Conventionally, a method has been employed for evaluating the resistance of a semiconductor integrated circuit to an external noise by providing the semiconductor integrated circuit with a power noise or external strong electromagnetic waves after the semiconductor integrated circuit is manufactured, in order to check the resistance of a semiconductor integrated circuit to an external noise. In case the semiconductor integrated circuit is less resistant to a noise, a de-coupling capacitor is inserted in the semiconductor integrated circuit or the circuit is modified to improve the resistance to a noise.
In this way, inspection on the resistance of a semiconductor integrated circuit to an external noise is performed after the circuit is manufactured. In case any problem occurs concerning an external noise during inspection, the entire semiconductor integrated circuit requires modification. This increases the design period.
The invention has been proposed in view of the foregoing situation and relates to a method for reducing electromagnetic wave disturbance while maintaining the high integration density and high-speed characteristics of an LSI circuit.
The invention aims at preventing malfunction caused by indirect EMS where an external noise enters the power source and malfunction caused by direct EMS caused by electromagnetic wave radiation as well as readily provide the layout of a reliable semiconductor integrated circuit device.
The invention aims at providing a method for readily identify the location in the design stage where circuit malfunction could be potentially caused by a noise, by obtaining the propagation of a noise waveform in a large-scale semiconductor integrated circuit.
Further, the invention aims at enhancing the resistance of a semiconductor integrated circuit to a noise before manufacturing the circuit by simulating the verification of circuit operation against a power noise.
In order to attain the foregoing object, a method for analyzing an external noise to a semiconductor integrated circuit according to the invention is characterized in that the method comprises an impedance extraction step of extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, an equivalent circuit creating step of creating an equivalent circuit from the impedance information, and an analysis step of supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.
According to such steps, an equivalent circuit is created from impedance information, a noise waveform is externally supplied to the equivalent circuit and the influence of the noise on the semiconductor integrated circuit is analyzed. It is thus possible to readily take high-accuracy EMS countermeasures.
The second aspect of the invention is characterized in that the analysis step includes a noise waveform supplying step of supplying a start point power noise waveform, a power noise waveform calculating step of obtaining power noise waveforms at the internal node points and terminals in the semiconductor integrated circuit, and an error section detecting step of obtaining the influence of an external noise on the semiconductor integrated circuit and detecting sections susceptible to an external noise entering the semiconductor integrated circuit.
With this configuration, it is possible to readily detect the sections susceptible to an external noise thus readily taking high-accuracy EMS countermeasures
The third aspect of the invention is characterized in that the equivalent circuit creating step comprises a functional block power equivalent circuit creating step of creating a degenerate impedance circuit of each functional block in a semiconductor integrated circuit from the impedance information and an inter-block power equivalent circuit creating step of creating a circuit for analyzing the inter-block power wiring in the semiconductor integrated circuit from the impedance information and that the analysis step uses as the equivalent circuit at least one of the degenerate impedance circuit and the circuit for analyzing the inter-block power wiring.
The fourth aspect of the invention is characterized in that the equivalent circuit creating step comprises a functional block power equivalent circuit creating step of creating a degenerate impedance circuit of each functional block in a semiconductor integrated circuit from the impedance information, an inter-block power equivalent circuit creating step of creating a circuit for analyzing the inter-block power wiring in the semiconductor integrated circuit from the impedance information and an external power equivalent circuit creating step of creating an a circuit for analyzing the power wiring external to the semiconductor integrated circuit from the impedance information, and that the analysis step uses as the equivalent circuit at least one of the degenerate impedance circuit, the circuit for analyzing the inter-block power wiring and the circuit for analyzing the power wiring external to the semiconductor integrated circuit.
According to the third and fourth aspects, it is readily possible to identify the sections susceptible to EMS by inputting a power noise waveform to the power line external to a semiconductor integrated circuit, analyzing the propagation of the power noise waveform through simulation, and obtaining a power waveform at each point in the semiconductor integrated circuit.
The fifth aspect of the invention is characterized in that the inter-block power equivalent circuit creating step is a step of creating the circuit for analyzing the inter-block power wiring by adding the impedance information on the inter-block power wiring to the degenerate impedance circuit created by the functional block power equivalent circuit creating step and that the analysis step uses as the equivalent circuit at least one of the degenerate impedance circuit and the circuit for analyzing the inter-block power wiring.
The sixth aspect of the invention is characterized in that the inter-block power equivalent circuit creating step is a step of creating the circuit for analyzing the inter-block power wiring by adding the impedance information on the inter-block power wiring to the degenerate impedance circuit created by the functional block power equivalent circuit creating step, that the external power equivalent circuit creating step is a step of configuring a circuit for analyzing the power wiring external to the semiconductor integrated circuit by creating a degenerate impedance circuit in the circuit for analyzing the inter-block power wiring and adding the impedance information external to the semiconductor integrated circuit to the degenerate impedance circuit, and that the analysis step uses as the equivalent circuit at least one of the degenerate impedance circuit, the circuit for analyzing the inter-block power wiring and the circuit for analyzing the power wiring external to the semiconductor integrated circuit.
According to the fifth and sixth aspects, a degenerate impedance circuit is used on top of the advantages of the third and fourth aspects. This simplifies the arithmetic operation and readily provides a reliable analysis. The seventh aspect of the invention is characterized in that the noise waveform supplying step is a step of supplying a start point power noise waveform to the power terminal in a circuit for analyzing the inter-block power wiring created from the impedance information and that the power noise waveform calculating step includes an inter-block power noise calculating step of obtaining an inter-block power noise waveform at each internal node point in the circuit for analyzing the inter-block power wiring as well as obtaining a block terminal power noise waveform at a terminal in each functional block and an intra-functional-block power noise waveform calculating step of obtaining a functional block power noise waveform at each node point in the functional block as well as obtaining an element terminal power noise waveform at the power terminal in each element by providing as input the block terminal power noise waveform to the impedance circuit in the functional block created from the impedance information, and identifies the circuit section expected to be susceptible to an external noise by using at least one of the block terminal power noise waveform, the inter-block power noise waveform, the functional block power noise waveform and the element terminal power noise waveform.
The eighth aspect of the invention is characterized in that the noise waveform supplying step is a step of supplying a start point power noise waveform to the power terminal in a circuit for analyzing the power wiring external to the semiconductor integrated circuit created from the impedance information and that the power noise waveform calculating step includes external power noise waveform calculating step of obtaining a terminal power noise waveform at the power terminal in a circuit for analyzing the inter-block power wiring created from the impedance information through the circuit for analyzing the power wiring external to the semiconductor integrated circuit, an inter-block power noise calculating step of obtaining an inter-block power noise waveform at each internal node point of the inter-block power wiring as well as obtaining a block terminal power noise waveform at a terminal in each functional block and an intra-functional-block power noise waveform calculating step of obtaining a functional block power noise waveform at each node point in the functional block as well as obtaining an element terminal power noise waveform at the power terminal of each element by providing as input the block terminal power noise waveform to the impedance circuit in the functional block, and identifies the circuit section expected to be susceptible to an external noise by using at least one of the terminal power noise waveform, the block terminal power noise waveform, the inter-block power noise waveform, the functional block power noise waveform and the element terminal power noise waveform.
With this configuration, it is possible to analyze a large-scale semiconductor integrated circuit by creating impedance models of the power wiring external to the semiconductor integrated circuit, inter-block power wiring in a semiconductor integrated circuit and block wiring in a semiconductor integrated circuit separately, and obtaining power noise waveforms in a layered step.
The ninth aspect of the invention is characterized in that the error section detecting step comprises an error check step of identifying the circuit sections that will cause an error due to an external noise by providing a power noise peak threshold for the power noise waveform and assuming an error when the threshold is exceeded thus performing an error check.
With this configuration, an error check is made in accordance with a predetermined threshold so that it is possible to effectively identify the circuit sections that will cause an error.
The tenth aspect of the invention is characterized in that the error section detecting step performs a noise check step of performing a noise check by providing a threshold at the power terminal in the circuit for analyzing the inter-block power wiring and assuming an error when the threshold is exceeded and performs the inter-block power noise waveform calculating step only when an error is determined.
With this configuration, the inter-block power noise waveform calculating step is performed only when an error is determined assuming that the threshold at the power terminal in the circuit for analyzing the inter-block power wiring is exceeded. This includes no useless steps and allows an efficient check.
The eleventh aspect of the invention is characterized in that the threshold at the power terminal in the circuit for analyzing the inter-block power wiring is the maximum among the thresholds for the terminal in the functional block in the semiconductor integrated circuit and inter-block power wiring.
With this configuration, the threshold at the power terminal in the circuit for analyzing the inter-block power wiring is set to the maximum among the thresholds for the terminal in the functional block in the semiconductor integrated circuit and inter-block power wiring. This prevents useless calculation and allows an efficient check.
The twelfth aspect of the invention is characterized in that the error section detecting step performs a noise check step of performing a noise check by providing a peak threshold for a power noise at each functional block in a semiconductor integrated circuit and assuming an error when the threshold is exceeded at the power terminal in the functional block and performs the intra-functional-block power noise waveform calculating step only when an error is determined.
With this configuration, the intra-block power noise waveform calculating step is performed only when an error is determined assuming that the threshold for a noise power peak for each functional block is exceeded. This includes no useless steps and allows an efficient check.
The thirteenth aspect of the invention is characterized in that the threshold for a power noise at the power terminal in each functional block is the maximum of the thresholds for the functional elements in each functional block and power wiring.
With this configuration, the threshold at the power terminal in the circuit for analyzing the inter-block power wiring is set to the maximum among the thresholds for the functional element in the semiconductor integrated circuit, the functional element in the functional block, and the power wiring. This prevents useless calculation and allows an efficient check.
The fourteenth aspect of the invention is characterized in that the error check step comprises a noise check step of performing a noise check by providing a peak threshold for a power noise at each functional element in a semiconductor integrated circuit and assuming an error when the power noise peak value has exceeded the threshold.
With this configuration, an error check is made in accordance with a predetermined threshold so that it is possible to effectively identify the circuit sections that will cause an error.
The fifteenth aspect of the invention is characterized in that the error check step comprises a noise check step of performing a noise check by providing a peak threshold for a power noise determined by the distance to an adjacent signal line and length of parallel wiring for the power wiring in each functional block or inter-block power wiring and assuming an error when the power noise peak value has exceeded the threshold at each internal node points of the power wiring.
With this configuration, the intra-block power noise waveform calculating step is performed only when an error is determined assuming that threshold for a noise power peak for the power wiring in each functional block or inter-block power wiring is exceeded. This includes no useless steps and allows an efficient check.
The sixteenth aspect of the invention is analysis apparatus, characterized in that the apparatus comprises extraction means for extracting impedance information on the power wiring in the target semiconductor integrated circuit or the power wiring in the semiconductor integrated circuit and the external power wiring of the semiconductor integrated circuit, equivalent circuit creating means for creating an equivalent circuit from the impedance information, and analysis means for supplying a noise waveform externally and analyzing the influence of the noise on the semiconductor integrated circuit.
With this configuration, an equivalent circuit is created from impedance information, a noise waveform is externally supplied to the equivalent circuit and the influence of the noise on the semiconductor integrated circuit is analyzed. It is thus possible to readily take high-accuracy EMS countermeasures.
The seventeenth aspect of the invention is characterized in that the analysis step comprises a step of obtaining a power waveform at the power terminal of each circuit element in the semiconductor integrated circuit, a calculating step of calculating the delay time of the circuit element based on the power waveform at the power terminal of the circuit element, and a timing verification step of determining whether the delay time of the circuit element is within an allowable range.
With this configuration, timing verification is made based on the calculated delay time in accordance with the power waveform at the power terminal of each circuit element. It is thus possible to readily perform high-accuracy verification.
The eighteenth aspect of the invention is characterized in that the analysis step comprises a step of obtaining a power waveform at the power terminal of each circuit element in the semiconductor integrated circuit, a calculating step of calculating the delay time of the circuit element based on the power waveform at the power terminal of the circuit element, and a timing verification step of determining whether the sum of the delay times of the series of circuit elements is within an allowable range.
With this configuration, it is possible to perform high-accuracy verification, on top of the advantage of the seventeenth aspect.
The nineteenth aspect of the invention is characterized in that the analysis step comprises a database creating step of calculating the variation amount in the delay time of a circuit element obtained when at least one of the input timing and peak value of the noise waveform of the power terminal is varied and creating a delay variation amount database based on the calculation result, and that the calculating step comprises a step of obtaining the variation amount of the delay time of the circuit element with respect to a desired noise waveform from the delay variation amount database.
The twentieth aspect of the invention is characterized in that the analysis step comprises a database creating step of calculating the variation amount in the delay time of a circuit element obtained when at least one of the input timing and peak value of the noise waveform of the power terminal is varied and creating a delay variation rate database by obtaining the calculation result as a rate to the delay time of the circuit element observed when no power noises are present, and that the calculating step comprises a step of obtaining the delay variation amount of the circuit element with respect to a desired noise, by multiplying the delay time of the circuit element observed when no power noises are present by the rate read from the delay variation rate database.
The twenty-first aspect of the invention is characterized in that the analysis step comprises a step of obtaining the delay variation amount of the series of circuit elements with the timing the power noise where the variation amount of each circuit element is the maximum is input to the series of circuit element, as the maximum delay amount of the series of circuit elements.
The twenty-second aspect of the invention is characterized in that the analysis step comprises a step of detecting a circuit section where a signal does not arrive within a time required for circuit operation due to a variation in the delay time of a circuit element caused by a power noise thus resulting in an unexpected circuit operation.
The twenty-third aspect of the invention is characterized by further comprising an error element detecting step of exploring a circuit element whose delay time is most affected by a power noise from the detected circuit section and detecting the circuit element as an error element.
The twenty-fourth aspect of the invention is characterized by further comprising are in forcing step of taking power noise hardening countermeasures on the error element.
The twenty-fifth aspect of the invention is characterized by further comprising a replacing step of replacing the circuit element assumed as an error element in the error element detecting step with a circuit element whose delay variation amount with respect to a power noise is smaller.
The twenty-sixth aspect of the invention is characterized by further comprising a replacing step of replacing the circuit element assumed as an error element in the error element detecting step with a circuit element which satisfies a constraint time.
The twenty-seventh aspect of the invention is characterized by further comprising a step of manufacturing a semiconductor device through error-free layout design based on the analysis result using an electromagnetic disturbance analysis method according any one of the first to twenty-sixth aspects.
With these configurations, the signal waveform at the power terminal of each circuit element in a semiconductor integrated circuit is obtained, then the input timing and peak value of a power noise at the power terminal of each circuit element in the semiconductor integrated circuit are obtained. A database may be created by simulation which calculates the variation amount of the delay time of the circuit element when the input timing and peak value of the power noise is varied. Based on the noise waveform at the power terminal of each circuit element and on the database of the delay time variation amount, the variation amount of the delay time of a circuit element may be calculated. Further, a circuit section, where a signal does not arrive within a time required for circuit operation due to a variation at the delay time of a circuit element caused by providing an arbitrary power noise thus resulting in an unexpected circuit operation, maybe detected. Noise tolerance maybe improved by changing a circuit element in order to satisfy the constraint time in the circuit section where an unexpected circuit operation occurs in case an arbitrary power noise is provided.
The twenty-eighth aspect of the invention is a method for analyzing an electromagnetic disturbance in an LSI circuit, characterized in that the method comprises a library storage step of calculating the noise threshold for changing the output result or internal state caused by a power noise and storing the noise threshold into a library and an analysis step of analyzing whether each of the circuit elements in the LSI circuit suffer from the influence of the power noise while referring to the library.
With this configuration, analysis is readily made with efficiency by storing the threshold into a library.
The twenty-ninth aspect of the invention is characterized in that the library storage step comprises a step of storing into a library any of the peak, width and shape functions or values of the voltage or current waveform that can pass through a circuit element.
The thirtieth aspect of the invention is characterized in that the library storage step comprises a step of storing into the library a noise threshold for a path on which a noise is input to the terminal of a circuit element and is output from the terminal of the circuit element or a path for changing the internal state.
With the configurations of the twenty-ninth and thirtieth aspects, it is possible to perform more efficient analysis.
The thirty-first aspect of the invention is characterized in that the analysis step comprises a step of analyzing a path to be input to the terminal of a circuit element and output from the terminal of the circuit element or to change the internal state.
The thirty-second aspect of the invention is characterized in that the analysis step comprises a recording step of recording path information.
The thirty-third aspect of the invention is characterized in that the recording step comprises a step of recording a circuit element where a noise is propagated.
The thirty-fourth aspect of the invention is characterized in that the recording step comprises a step of recording a register element where a noise is propagated.
The thirty-fifth aspect of the invention is characterized in that the recording step comprises a step of recording a damage that results when a circuit element where a noise is propagated is virtually changed to a circuit element with different drive capability.
The thirty-sixth aspect of the invention is characterized in that the recording step comprises a step of recording a circuit element susceptible to a noise on the path.
The thirty-seventh aspect of the invention is characterized in that the analysis step comprises a step of calculating the power noise by analyzing electromagnetic wave.
The thirty-eighth aspect of the invention is characterized in that the analysis step comprises a step of recording a circuit element susceptible to a noise on the path entering a specified circuit element.
The thirty-ninth aspect of the invention is characterized in that the analysis step comprises a step of recording a circuit element susceptible to a noise on the path entering a register element.
With the configurations of the thirty-first through thirty-ninth aspects, efficiency of counter measure processing is considerably improved by detecting and recording a section susceptible to an electromagnetic disturbance more easily.
The fortieth aspect of the invention is analysis apparatus for analyzing an electromagnetic disturbance in an LSI circuit, characterized in that the apparatus comprises a library storage step of calculating the noise threshold for changing the output result or internal state depending on a power noise and storing the noise threshold into a library, and an analysis step of analyzing whether each of the circuit elements in the LSI circuit suffer from the influence of the power noise while referring to the library.
With this configuration, analysis is readily made with efficiency by storing the threshold into a library.
The forty-first aspect of the invention is characterized by comprising a step of analyzing an electromagnetic disturbance in an LSI circuit, a sorting step of sorting blocks or instances that need countermeasures and a countermeasure step of taking countermeasures to erase a power noise on each block or instance.
With this configuration, blocks or instances that need countermeasures are sorted so that it is possible to efficiently take countermeasures in this order.
The forty-second aspect of the invention comprises a step of analyzing EMS of the block or instance after the countermeasure step, characterized in that the countermeasure step and analysis step are repeated until the influence of the power noise is found below a predetermined value in the analysis step.
With this configuration, the countermeasure step and analysis step are repeated until the influence of the power noise is found below a predetermined value in the analysis step so that it is possible to take reliable countermeasures efficiently.
The forty-third aspect of the invention is characterized in that the countermeasure step is a step of inserting a delay adjustment element for performing delay adjustment so that a switching element will become highly resistant with the timing a current including a noise enters the switching element and an RC filter circuit formed by the switching element and a capacitance element.
With this configuration, it is possible to perform removal of noise only through adjustment of a switching element and a capacitance element to be inserted.
The forty-fourth aspect of the invention is characterized in that the countermeasure step is a step of inserting an inductor.
The forty-fifth aspect of the invention is characterized in that the countermeasure step is a step of adjusting the power wiring length distance.
The forty-sixth aspect of the invention is characterized in that the countermeasure step is a step of changing the cell rank so that the drive capability of the cell with sufficient timing will be reduced.
With the foregoing configurations, it is possible to efficiently perform removal of noise.
The forty-seventh aspect of the invention is characterized by comprising means for analyzing an electromagnetic disturbance in an LSI circuit, sorting means for sorting blocks or instances that need countermeasures and countermeasure means for taking countermeasures to erase a power noise on each block or instance in accordance with the order arranged by the sorting means.
With this configuration, blocks or instances that need countermeasures are sorted so that it is possible to efficiently take countermeasures in this order.
The forty-eighth aspect of the invention comprises means for analyzing EMS of the block or instance that undertook countermeasures in the countermeasure means, characterized in that the countermeasure step and analysis step are repeated until the influence of the power noise is found below a predetermined value in the analysis step.
With this configuration, the countermeasure step and analysis step are repeated until the influence of the power noise is found below a predetermined value in the analysis means, so that it is possible to perform efficient and reliable processing. With this configuration, it is possible to detect an increase in the power consumption observed when for example a buffer is replaced with one having larger drive capability.
The forty-ninth aspect of the invention is characterized by comprising a display step of highlighting cells susceptible to a noise and paths connecting the cells as analyzed in the analysis step.
The fiftieth aspect of the invention is characterized by comprising a display step of highlighting register cells such as memory cells.
The fifty-first aspect of the invention is characterized by comprising a display step of displaying information on cells that were found susceptible to a noise and should be replaced in the analysis step.
The fifty-second aspect of the invention is characterized by comprising a virtual display step of displaying parameters renewed for each cell virtually changed based on the information on cells that were analyzed to be replaced with spare in the analysis step.
The fifty-third aspect of the invention is characterized by comprising a sorting step of sorting blocks or instances determined requiring countermeasures in the analysis step.
The fifty-fourth aspect of the invention is characterized by comprising a countermeasure sorting step of sorting countermeasures to take on blocks or instances determined to require countermeasures in the analysis step.
With the configurations of the forty-ninth through fifty-fourth aspects, EMS analysis and corresponding countermeasures take place. It is possible to sequentially display the steps and display which countermeasures are to be taken on which objects and resulting changes. This makes it possible to take countermeasures more efficiently.
In this way, favorable EMS countermeasures are taken thus making it possible to provide automatically and with high speed the reliable layout structure of a semiconductor integrated circuit.